HMT325U7CFR8A Datasheet, PDF (17/52 Pages) Hynix Semiconductor – DDR3L SDRAM Unbuffered DIMMs Based on 2Gb C-Die

AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below.
DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 50 in “DDR3L Device Opera-
tion”) as well as derating tables Table 46 in “DDR3L Device Operation” depending on Vih/Vil AC levels.
Single Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
DDR3L-800/1066
Min
Max
DDR3L-1333/1600
Min
Max
Unit Notes
VIH.DQ(DC90) DC input logic high
VIL.DQ(DC90) DC input logic low
VIH.DQ(AC160) AC input logic high
VIL.DQ(AC160) AC input logic low
VIH.DQ(AC135) AC Input logic high
VIL.DQ(AC135) AC input logic low
VIH.DQ(AC130) AC Input logic high
VIL.DQ(AC130) AC input logic low
V_RefDQ(DC)
Reference Voltage
for DQ, DM inputs
Vref + 0.09
VSS
Vref + 0.160
Note2
Vref + 0.135
Note2
-
-
0.49 * VDD
VDD
Vref - 0.09
Note2
Vref - 0.160
Note2
Vref - 0.135
-
-
0.51 * VDD
Vref + 0.09
VSS
-
-
Vref + 0.135
Note2
-
-
0.49 * VDD
VDD
Vref - 0.09
-
-
Note2
Vref - 0.135
-
-
0.51 * VDD
V1
V1
V 1, 2, 5
V 1, 2, 5
V 1, 2, 5
V 1, 2, 5
V 1, 2, 5
V 1, 2, 5
V 3, 4
Notes:
1. Vref = VrefDQ (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 29.
3. The ac peak noise on V_Ref may not allow V_Ref to deviate from V_RefDQ(DC) by more than +/-1% VDD (for reference:
approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on
page 16) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) apply. The 1.5V levels (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) do not apply when the device is
operated in the 1.35 voltage range.
Rev. 1.1 / Jul. 2013
17