HMT325S6CFR8C Datasheet, PDF (5/48 Pages) Hynix Semiconductor – DDR3 SDRAM Unbuffered SODIMMs Based on 2Gb C-die

Pin Descriptions
Pin Name
CK[1:0]
CK[1:0]
CKE[1:0]
RAS
CAS
Description
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Num
ber
2
2
2
1
1
WE
Write Enable
1
S[1:0]
Chip Selects
2
A[9:0],A11,
A[15:13]
Address Inputs
14
A10/AP
A12/BC
Address Input/Autoprecharge 1
Address Input/Burst chop
1
BA[2:0]
SDRAM Bank Addresses
3
ODT[1:0] On Die Termination Inputs
2
SCL
Serial Presence Detect (SPD)
Clock Input
1
SDA
SPD Data Input/Output
1
SA[1:0]
SPD Address Inputs
2
Pin Name
DQ[63:0]
DM[7:0]
DQS[7:0]
DQS[7:0]
EVENT
TEST
RESET
Description
Num
ber
Data Input/Output
64
Data Masks
8
Data strobes
8
Data strobes, negative line
8
Temperature event pin
1
Logic Analyzer specific test pin (No
connect on SODIMM)
1
Reset Pin
1
V_DD
Core and I/O Power
18
V_SS
Ground
52
V_REFDQ
V_REFCA
V_TT
V_DDSPD
NC
Input/Output Reference
Termination Voltage
SPD Power
Reserved for future use
1
1
2
1
2
Total: ₂₀₄
Rev. 1.0/Sep. 2012
5