HMT325S6CFR8C Datasheet, PDF (37/48 Pages) Hynix Semiconductor – DDR3 SDRAM Unbuffered SODIMMs Based on 2Gb C-die

Symbol
Precharge Standby Current
Description
I_DD2N
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details:
see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
I_{DD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all}
banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
I_DD2P0
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit^c)
Precharge Power-Down Current Fast Exit
I_DD2P1
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit^c)
Precharge Quiet Standby Current
I_DD2Q
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0
Active Standby Current
I_DD3N
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see
Table 5.
Active Power-Down Current
I_DD3P
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0
Rev. 1.0/Sep. 2012
37