HMT164S6BFR6C-G7 Datasheet, PDF (45/51 Pages) Hynix Semiconductor – 204pin DDR3 SDRAM SODIMMs

HMT164S6BFR6C
HMT112S6BFR6C
HMT125S6BFR8C
Notes:
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection
of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the
DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC
standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns],
rounding up to the next ‘Supported CL’.
3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG) down to the
next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to
CLSELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory
feature. Refer to supplier’s data sheet and SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
8. It is not a mandatory bin. Refer to supplier’s data sheet and/or the DIMM SPD information.
9. If it’s supported, the minimum tAA/tRCD/tRP that this device support is 13.125ns. Therefore, In Module application,
tAA/tRCD/tRP should be programed with minimum supported values. For example, DDR3-1333H supporting down-
shift to DDR3-1066F should program SPD as 13.125ns for tAAmin(Byte16)/tRCDmin(Byte18)/tRP(Byte20). DDR3-
1600K supporting down-shift to DDR3-1333H and/or DDR3-1066F should program SPD as 13.125ns for
tAAmin(Byte16)/tRCDmin(Byte18)/tRP(Byte20).
Rev. 0.5 / Sep. 2009
45