HY51VS18163HG Datasheet, PDF (4/12 Pages) Hynix Semiconductor – 1M x 16Bit EDO DRAM

HY51V(S)18163HG/HGL
Truth Table
/RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
H to L
H to L
H to L
/LCAS
D
L
H
L
L
H
L
L
H
L
L
H
L
H
L
L
/UCAS
D
H
L
L
H
L
L
H
L
L
H
L
L
L
H
L
/WE
D
H
H
H
L
L
L
L
L
L
H to L
H to L
H to L
D
D
D
L
H
H
D
/OE
D
L
L
L
D
D
D
H
H
H
L to H
L to H
L to H
D
D
D
D
Output
Open
Valid
Valid
Valid
Open
Open
Open
Undefined
Undefined
Undefined
Valid
Valid
Valid
Open
Open
Open
Open
L
L
L
H
H
Open
Operation
Standby
Lower byte
Upper byte
Word
Read cycle
Lower byte
Upper byte
Word
Early write cycle
Lower byte
Upper byte
Word
Delayed write cycle
Lower byte
Upper byte
Word
Read-modify-write
Cycle
Word
Word
Word
CBR refresh
or
Self refresh
(L-series)
Word
/RAS only refresh
cycle
Read cycle
(Output disabled)
Notes
1 ,3
1, 3
1, 2, 3
1, 2, 3
1, 3
1, 3
1, 3
1, 3
Notes :
1. H : High ( inactive) L : Low ( active) D : H or L
2. tWCS >= 0ns Early write cycle
twcs < 0ns Delayed write cycle
3. Mode is determined by the OR function of the /UCAS and /LCAS (mode is set by earliest of /UCAS and /LCAS
active edge and reset by the latest of /UCAS and /LCAS inactive edge), However write operation and output
High-Z control are done independently by each /UCAS, /LCAS
ex) if /RAS = H to L, /UCAS = H, /LCAS = L, then /CAS-before-/RAS refresh cycle is selected
Rev.0.1/Apr.01
4