HY51VS18163HG Datasheet, PDF (11/12 Pages) Hynix Semiconductor – 1M x 16Bit EDO DRAM

HY51V(S)18163HG/HGL
17. Access time is determined by the longest among tAA or tCAC or tACP
18. In delayed write or read-modify-write cycels, OE must disable output buffer prior to applying data to the
device, After /RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance)
If tOEH < tCWL, invalid data will be out at each I/O
19. When both /UCAS and /LCAS go low at the same time, all 16 bit data are written into the device
/UCAS and /LCAS cannot be staggered within the same write / read cycles.
20. All the Vcc and Vss pins shall be supplied with the same voltages
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of /UCAS
or /LCAS.
22. tCRP, tCHR, tRCH, tACP and tCPW are determined by the later rising edge of /UCAS or /LCAS.
23. tCWL, tDH, tDS and tCSH should be satisfied by both /UCAS and /LCAS
24. tCP is determined by that time the both /UCAS and /LCAS are high.
25. tHPC(min) can be achieved during a series of EDO page mode write cycles or EDO mode write cycles
It both write and read operation are mixed in a EDO mode /RAS cycle(EDO mode mix cycle(1,2))
minimum value of /CAS cycle(tCAS+tCP+2tT) becomes greater than the specified tHPC(min) value.
The value of /CAS cycle time of mixed EDO mode is shown in EDO mode mix cycle (1) and (2)
26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained
When output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line
noise, which causes to degrade VIH min / VIL max level
27. Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS.
Hold time and turn off time are specified by the timing specification of later rising edge of /RAS and
/CAS between tOHR and tOH, and between tOFR and tOFF
28. EDO High-Z control by /OE or /WE. /OE rising edge disables data outputs. When /OE goes high
during /CAS high, the data will not come out until next /CAS access. When /WE goes low during
/CAS high, the data will not come out until next /CAS access
29. Please do not use tRASS timing, 10us<=tRASS<=100us. During this period, The device is in transition
state from normal operation mode to self refresh mode. If tRASS>=100us, then RAS
30. H or L ( H : VIH(min) <=VIN <= VIH(max), L : VIL(min) <= VIN <= VIL(max))
Rev.0.1/Apr.01
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