H5TQ2G63BFR Datasheet, PDF (36/93 Pages) Hynix Semiconductor – 2Gb DDR3 SDRAM

H5TQ2G63BFR
5.4 Slew Rate Definitions for Single Ended Input Signals
5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VRef and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VRef and the first crossing of VIL (AC) max.
5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max
and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew
rate between the last crossing of VIH (DC) min and the first crossing of VRef.
Single-Ended Input Slew Rate Definition
Description
Measured
Min
Max
Defined by
VIH (AC) min-Vref
Input slew rate for rising edge
Vref
VIH (AC) min
Delta TRS
Input slew rate for falling edge
Vref
VIL (AC) max
Vref-VIL (AC) max
Delta TFS
Input slew rate for rising edge VIL (DC) max
Vref
Vref-VIL (DC) max
Delta TFH
Input slew rate for falling edge VIH (DC) min
Vref
VIH (DC) min-Vref
Delta TRH
Input Nominal Slew Rate Definition for Single-Ended Signals
Applicable for
Setup
(tIS, tDS)
Hold
(tIH, tDH)
P art A : S et u p
D e lta T R S
P a rt B : H o ld
D e lta T F S
D e lta T R H
D e lta T F H
F ig u re 8 2 ? In p u t N o m in a l S le w R a te D e fin itio n fo r S in g le -E n d e d S ig n a ls
v IH ( A C ) m in
v IH ( D C )m in
vR e fD Q o r
v R e fC A
vIH (D C )m ax
vIH (A C )m ax
v IH ( A C ) m in
v IH ( D C ) m in
vR e fD Q o r
v R e fC A
vIH (D C )m ax
vIH (A C )m ax
Rev. 0.5 / Aug. 2010
36