H5TQ2G63BFR Datasheet, PDF (14/93 Pages) Hynix Semiconductor – 2Gb DDR3 SDRAM

H5TQ2G63BFR
1.6.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to suquential or interleaved order. The burst type is selected via bit A3
as shown is Figure 6. The ordering of accesses within a burst is determined by the burst length, burst type, and the start-
ing column address as shown in Table 2. The burst length is defined by bits A0-A1. Burst length options include fixed
BC4, fixed BL8, and ‘on the fly’ which allows BC4 or BL8 to be selected coincident with the registration of a Read or Write
command via A12/BC.
Table 2. Burst Type and Burst Order
Burst
Length
4
Chop
8
READ/
WRITE
Starting
Column
ADDRESS
(A2,A1,A0)
burst type = Sequential
(decimal)
A3 = 0
burst type = Interleaved
(decimal)
A3 = 1
Notes
READ
000
0,1,2,3,T,T,T,T
0,1,2,3,T,T,T,T
1,2,3
001
1,2,3,0,T,T,T,T
1,0,3,2,T,T,T,T,
1,2,3
010
2,3,0,1,T,T,T,T
2,3,0,1,T,T,T,T
1,2,3
011
3,0,1,2,T,T,T,T
3,2,1,0,T,T,T,T
1,2,3
100
4,5,6,7,T,T,T,T
4,5,6,7,T,T,T,T
1,2,3
101
5,6,7,4,T,T,T,T
5,4,7,6,T,T,T,T
1,2,3
110
6,7,4,5,T,T,T,T
6,7,4,5,T,T,T,T
1,2,3
111
7,4,5,6,T,T,T,T
7,6,5,4,T,T,T,T
1,2,3
WRITE
0,V,V
0,1,2,3,X,X,X,X
0,1,2,3,X,X,X,X
1,2,4,5
1,V,V
4,5,6,7,X,X,X,X
4,5,6,7,X,X,X,X
1,2,4,5
READ
000
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2
001
1,2,3,0,5,6,7,4
1,0,3,2,5,4,7,6
2
010
2,3,0,1,6,7,4,5
2,3,0,1,6,7,4,5
2
011
3,0,1,2,7,4,5,6
3,2,1,0,7,6,5,4
2
100
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
2
101
5,6,7,4,1,2,3,0
5,4,7,6,1,0,3,2
2
110
6,7,4,5,2,3,0,1
6,7,4,5,2,3,0,1
2
111
7,4,5,6,3,0,1,2
7,6,5,4,3,2,1,0
2
WRITE
V,V,V
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2,4
Notes:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock
cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled
in by two clocks. In case of burst length being selected on-the-fly via A12/BC#, the internal write opera-
tion starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly
control, the starting point for tWR and tWTR will not be pulled in by two clocks.
2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
3. T: Ouput driver ofr data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Don’t Care.
Rev. 0.5 / Aug. 2010
14