HY5DU12822B Datasheet, PDF (34/37 Pages) Hynix Semiconductor – 512Mb DDR SDRAM

HY5DU12422B(L)TP
HY5DU12822B(L)TP
HY5DU121622B(L)TP
-Continue:
Parameter
Symbol
Input Setup Time
(fast slew rate)
Input Hold Time
(fast slew rate)
Input Setup Time
(slow slew rate)
Input Hold Time
(slow slew rate)
Input Pulse Width
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of
DQS-In
DQSfalling edge to CK
setup time
DQS falling edge hold time from CK
Data-In Setup Time to DQS-
In (DQ & DM)
Data-in Hold Time to DQS-In
(DQ & DM)
DQ & DM Input Pulse Width
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Exit Self Refresh to Any
Execute Command
Average Periodic Refresh
Interval
tIS
tIH
tIS
tIH
tIPW
tDQSH
tDQSL
tDQSS
tDSS
tDSH
tDS
tDH
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
tXSC
tREFI
DDR266A
Min
Max
0.9
-
0.9
-
1.0
-
1.0
-
2.2
-
0.35
-
0.35
-
0.75
1.25
0.2
0.2
0.5
-
0.5
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
DDR266B
Min
Max
0.9
-
0.9
-
1.0
-
1.0
-
2.2
-
0.35
-
0.35
-
0.75
1.25
0.2
0.2
0.5
-
0.5
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
DDR200
Min
Max
1.1
-
1.1
-
1.1
-
1.1
-
2.5
-
0.35
-
0.35
-
0.75
1.25
0.2
0.2
0.6
-
0.6
-
2
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
UNIT NOTE
ns
2,3,5,
6
ns
ns
2,4,5,
6
ns
ns
6
CK
CK
CK
CK
CK
ns
6,7,
11,12,
ns
13
ns
CK
CK
CK
CK
CK
CK
CK
8
us
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
Rev. 0.1 / May 2004
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