HY5DU12822B Datasheet, PDF (25/37 Pages) Hynix Semiconductor – 512Mb DDR SDRAM

HY5DU12422B(L)TP
HY5DU12822B(L)TP
HY5DU121622B(L)TP
DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
128Mx4
Parameter Symbol
Test Condition
Speed
Unit Note
-J -M -K -H -L
Operating Current
IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
140
130
120
120
100
mA
once per clock cycle
Operating Current
IDD1
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per clock
cycle
180 160 150 150 140 mA
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
mA
Idle Standby
Current
IDD2N Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
35
mA
Idle Standby
Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once
per clock cycle.
VIN=VREF for DQ, DQS and DM
35
mA
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref for
DQ, DQS and DM
25
mA
Active Power
Down
Standby Current
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
12
mA
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
Active Standby
Current
IDD3N
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock
45
cycle; Address and other control inputs changing once
40
mA
per clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
240 200 200 200 170
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
240 200 200 200 170 mA
Auto Refresh
Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed
280 260 260 260 240
refresh
Self Refresh
Current
IDD6
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Normal
Low Power
5
mA
2.5
mA
Operating Current
- Four Bank
Operation
IDD7
Four bank interleaving with BL=4, Refer to the
following page for detailed test condition
460 380 380 380 300 mA
Random Read
Current
IDD7A
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
mA, 100% DQ, DM and DQS inputs changing twice per 460 380 380 380 300 mA
clock cycle; 100% addresses changing once per clock
cycle
Rev. 0.1 / May 2004
25