HY5DU12822B Datasheet, PDF (33/37 Pages) Hynix Semiconductor – 512Mb DDR SDRAM

HY5DU12422B(L)TP
HY5DU12822B(L)TP
HY5DU121622B(L)TP
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Active to Read with Auto
Precharge Delay
Row Address to Column Address
Delay
Row Active to Row Active Delay
Column Address to Column
Address Delay
Row Precharge Time
Write Recovery Time
Internal Write to Read Command
Delay
Auto Precharge Write Recovery +
Precharge Time
System Clock Cycle
Time
CL = 2.5
CL = 2
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge
Skew
DQS-Out edge to Clock edge
Skew
DQS-Out edge to Data-Out edge
Skew
Data-Out hold time from DQS
Clock Half Period
Data Hold Skew Factor
Valid Data Output Window
Data-out high-impedance
window from CK,/CK
Data-out low-impedance window
from CK, /CK
Symbol
tRC
tRFC
tRAS
tRAP
tRCD
tRRD
tCCD
tRP
tWR
tWTR
tDAL
tCK
tCH
tCL
tAC
tDQSCK
tDQSQ
tQH
tHP
tQHS
tDV
tHZ
tLZ
DDR266A
Min
Max
65
-
75
-
45
120K
tRCD or
tRPmin
-
DDR266B
Min
Max
65
-
75
-
45
120K
tRCD or
tRPmin
-
DDR200
Min
Max
70
-
80
-
50
120K
tRCD or
tRPmin
-
20
-
20
-
20
-
15
-
15
-
15
-
1
-
1
-
1
-
20
-
20
-
20
-
15
-
15
-
15
-
1
-
1
-
1
-
(tWR/tCK)
+
(tRP/tCK)
7.5
7.5
0.45
0.45
-
12
12
0.55
0.55
(tWR/tCK)
+
(tRP/tCK)
7.5
10
0.45
0.45
-
12
12
0.55
0.55
(tWR/tCK)
+
(tRP/tCK)
8.0
10
0.45
0.45
-
12
12
0.55
0.55
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.75
0.75
-
0.5
-
0.5
-
0.6
tHP
-tQHS
-
min
(tCL,tCH
-
)
-
0.75
tQH-tDQSQ
tHP
-tQHS
-
min
(tCL,tCH
-
)
-
0.75
tQH-tDQSQ
tHP
-tQHS
-
min
(tCL,tCH
-
)
-
0.75
tQH-tDQSQ
-0.75
0.75
-0.75
0.75
-0.8
0.8
-0.75
0.75
-0.75
0.75
-0.8
0.8
UNI
T
ns
ns
ns
ns
ns
ns
CK
ns
ns
CK
CK
ns
ns
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
16
15
1,10
1,9
10
17
17
Rev. 0.1 / May 2004
33