HY5DU28422ET Datasheet, PDF (31/35 Pages) Hynix Semiconductor – 128Mb DDR SDRAM

HY5DU28422ET
HY5DU28822ET
HY5DU281622ET
-continued-
Parameter
Symbol
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Input Pulse Width
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
tIS
tIH
tIS
tIH
tIPW
tDQSH
tDQSL
tDQSS
tDS
tDH
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
tXSC
tREFI
DDR266A
Min Max
0.9
-
0.9
-
1.0
-
1.0
-
2.2
0.35
-
0.35
-
0.75 1.25
0.5
-
0.5
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
15.6
DDR266B
Min Max
0.9
-
0.9
-
1.0
-
1.0
-
2.2
0.35
-
0.35
-
0.75 1.25
0.5
-
0.5
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
15.6
DDR200
Min Max
Unit
Note
1.1
-
ns 2,3,5,6
1.1
-
ns 2,3,5,6
1.1
-
ns 2,4,5,6
1.1
-
ns 2,4,5,6
2.5
-
ns
6
0.35
-
CK
0.35
-
CK
0.75 1.25 CK
0.6
-
ns
6,7,
0.6
-
ns ^11~13
2
-
ns
0.9
1.1 CK
0.4
0.6 CK
0
-
CK
0.25
-
CK
0.4
0.6 CK
2
-
CK
200
-
CK
8
-
15.6 us
Rev. 0.5 /Apr. 2006
31