HY5DU28422ET Datasheet, PDF (15/35 Pages) Hynix Semiconductor – 128Mb DDR SDRAM

HY5DU28422ET
HY5DU28822ET
HY5DU281622ET
CKE FUNCTION TRUTH TABLE
Current
State
CKEn-
1
CKEn
/CS
/RAS /CAS
/WE /ADD
Action
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit self refresh, enter idle after tSREX
L
SELF
REFRESH¹
L
L
H
L
H
L
H
L
H
H
H
H
H
L
H
L
X
X
Exit self refresh, enter idle after tSREX
X
ILLEGAL
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue self refresh
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit power down, enter idle
L
H
L
H
H
H
X
POWER
DOWN²
L
H
L
H
H
L
X
L
H
L
H
L
X
X
Exit power down, enter idle
ILLEGAL
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue power down mode
H
H
X
X
X
X
X
See operation command truth table
H
L
L
L
L
H
X
Enter self refresh
H
L
H
X
X
X
X
Exit power down
H
ALL BANKS
IDLE⁴
H
H
L
L
L
L
L
L
H
H
H
X
H
H
L
X
H
L
X
X
Exit power down
ILLEGAL
ILLEGAL
H
L
L
L
H
X
X
ILLEGAL
H
L
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
H
H
X
X
X
X
X
See operation command truth table
ANY STATE
OTHER
H
L
X
X
X
X
X
ILLEGAL⁵
THAN
ABOVE
L
H
X
X
X
X
X
INVALID
L
L
X
X
X
X
X
INVALID
Note:
When CKE=L, all DQ and DQS must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CLK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CLK may cause malfunction of any bank which is in active state.
Rev. 0.5 /Apr. 2006
15