HY5DU28422DT Datasheet, PDF (31/33 Pages) Hynix Semiconductor – 128Mb-S DDR SDRAM

HY5DU28422D(L)T
HY5DU28822D(L)T
HY5DU281622D(L)T
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be
guaranteed by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, are
required for READ command to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
For other commands, time interval of tRFC+2~5ns is required after Self Refresh Exit command.
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the
device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS
consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern
effects and p-channel to n-channel variation of the output drivers.
11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
V/ns
0.5
0.4
0.3
Delta tDS
ps
0
+100
+170
Delta tDH
ps
0
+75
+150
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is
flat below VREF +/-310mV for a duration of up to 2ns.
I/O Input Level
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where
the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For
example, if slew rate 1 = 0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps
ps
0
0
0
+/-0.25
+50
+50
+/- 0.5
+100
+100
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
15. tDAL = 2 clocks + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest
integer.
16. tCK is equal to the actual system clock cycle time.
Example: For DDR400(D4) at CL=3 and tCK = 5 ns,
tDAL = (15 ns / 5ns) + (18 ns / 5 ns) = (3.0) + (3.6)
Round up each non-integer to the next highest integer: = (3) + (4), tDAL = 7 clocks
17. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK.
Rev. 0.0 / Apr. 2003
31