HY5DU28422DT Datasheet, PDF (26/33 Pages) Hynix Semiconductor – 128Mb-S DDR SDRAM

HY5DU28422D(L)T
HY5DU28822D(L)T
HY5DU281622D(L)T
DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
8Mx16
Parameter Symbol
Test Condition
Operating Current
Operating Current
Precharge Power
Down Standby
Current
Idle Standby Current
Idle Standby Current
Idle Quiet Standby
Current
Active Power Down
Standby Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current -
Four Bank Operation
Random Read
Current
IDD0
IDD1
IDD2P
IDD2N
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
IDD7A
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
clock cycle
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once per
clock cycle.
VIN=VREF for DQ, DQS and DM
/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses
and other control inputs stable, Vin=Vref for DQ, DQS and
DM
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock
cycle
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Normal
Low Power
Four bank interleaving with BL=4, Refer to the following
page for detailed test condition
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA,
100% DQ, DM and DQS inputs changing twice per clock
cycle; 100% addresses changing once per clock cycle
Speed
Unit Note
-D4 -D43
120
mA
120
mA
10
mA
60
mA
60
mA
50
mA
10
mA
65
mA
170
mA
190
180
2
mA
1
mA
260
mA
260
mA
Rev. 0.0 / Apr. 2003
26