HY5DU28422DT Datasheet, PDF (27/33 Pages) Hynix Semiconductor – 128Mb-S DDR SDRAM

HY5DU28422D(L)T
HY5DU28822D(L)T
HY5DU281622D(L)T
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Typical Case : VDD = 2.6V, T=25 ^oC
2. Worst Case : VDD = 2.7V, T= 0 ^oC
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
4. Timing patterns
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random add
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Typical Case : VDD = 2.6V, T=25 ^oC
2. Worst Case : VDD = 2.7V, T= 0 ^oC
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.0 / Apr. 2003
27