HY57V561620C Datasheet, PDF (3/12 Pages) Hynix Semiconductor – 4 Banks x 4M x 16Bit Synchronous DRAM

FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Internal Row
Counter
HY57V561620C(L)T(P)
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
Row Active
Row
Pre
Decoders
Column
Active
Column
Pre
Decoders
4Mx16 Bank 3
4Mx16 Bank 2
4Mx16 Bank 1
4Mx16 Bank 0
Memory
Cell
Array
Y decoders
DQ0
DQ1
DQ14
DQ15
Bank Select
Column Add
Counter
A0
Address
A1
Register
Burst
Counter
A12
BA0
BA1
Mode Registers
CAS Latency
Data Out Control ^{Pipe Line Control}
Rev. 0.5 / June 2004
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