HY57V561620C Datasheet, PDF (1/12 Pages) Hynix Semiconductor – 4 Banks x 4M x 16Bit Synchronous DRAM

HY57V561620C(L)T(P)
4 Banks x 4M x 16Bit Synchronous DRAM
DESCRIPTION
The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16.
HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch (Leaded Package or Lead Free Package)
• All inputs and outputs referenced to positive edge of system
clock
• Data mask function by UDQM, LDQM
• Internal four banks operation
• Auto refresh and self refresh
• 8192 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY57V561620C(L)T(P)-6
HY57V561620C(L)T(P)-7
HY57V561620C(L)T(P)-K
HY57V561620C(L)T(P)-H
HY57V561620C(L)T(P)-8
HY57V561620C(L)T(P)-P
HY57V561620C(L)T(P)-S
Clock Frequency
166MHz
143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power
(Normal)
/
Low Power
Organization
4Banks x 4Mbits x16
Interface 400mil 54pin TSOP II
LVTTL
(Leaded)
/
Lead Free
Note :
1. HY57V561620CT Series : Nomal power & Leaded 54Pin TSOP II
2. HY57V561620CLT Series : Low power & Leaded 54Pin TSOP II
3. HY57V561620CTP Series : Nomal power & Lead Free 54Pin TSOP II
4. HY57V561620CLTP Series : Low power & Lead Free 54Pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.5 / June 2004
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