HY5DU283222Q Datasheet, PDF (25/27 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222Q
Parameter
4
Symbol
Min Max
Write DQS High Level Width
tDQSH 0.4
0.6
Write DQS Low Level Width
tDQSL 0.4
0.6
Clock to First Rising edge of DQS-In
tDQSS 0.75 1.25
Data-In Setup Time to DQS-In (DQ & DM) tDS 0.45
-
Data-In Hold Time to DQS-In (DQ & DM) tDH 0.45
-
Read DQS Preamble Time
tRPRE 0.7
1.1
Read DQS Postamble Time
tRPST 0.4
0.6
Write DQS Preamble Setup Time
tWPRES 0
-
Write DQS Preamble Hold Time
tWPREH 1.5
-
Write DQS Postamble Time
tWPST 0.4
0.6
Mode Register Set Delay
tMRD
2
-
Exit Self Refresh to Any Execute
Command
tXSC 200
-
Average Periodic Refresh Interval
tREFI
-
7.8
45
Min Max
0.4 0.6
0.4 0.6
0.75 1.25
0.45
-
0.45
-
0.8 1.1
0.4 0.6
0
-
1.5
-
0.4 0.6
2
-
200
-
-
7.8
5
Min Max
0.4 0.6
0.4 0.6
0.75 1.25
0.45
-
0.45
-
0.8 1.1
0.4 0.6
0
-
1.5
-
0.4 0.6
2
-
200
-
-
7.8
55
Min Max
Unit Note
0.4 0.6 CK
0.4 0.6 CK
0.75 1.25 CK
0.45
- ns 4
0.45
- ns 4
0.8 1.1 CK
0.4 0.6 CK
0
- ns
1.5
- ns
0.4 0.6 CK
2
- CK
200
- CK 5
-
7.8 us
Note :
1. tRCD/tRP of 3 Clock at only single bank operation supported.
2. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
3. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
4. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM(0~3).
5. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
6. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
7. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
8. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-
sitions through the DC region must be monotonic.
Rev. 1.2/Oct. 02
25