HY5DU283222Q Datasheet, PDF (24/27 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222Q
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
4
Symbol
Min Max
45
Min Max
5
Min Max
55
Min Max
Unit Note
Row Cycle Time
55
-
60.5
- ns
tRC
60
-
63
-
50
-
55
- ns 1
Auto Refresh Row Cycle Time
tRFC
68
-
67.5
-
65
-
66
- ns
Row Active Time
tRAS
40 120K 40.5 120K 35 120K 38.5 120K ns
Row Address to Column Address Delay
for Read
tRCDRD
5
-
5
-
4
3
-
-
4
3
- CK
- CK 1
Row Address to Column Address Delay
for Write
tRCDWR
3
-
3
-
2
-
2
- CK
Row Active to Row Active Delay
tRRD
2
-
2
-
2
-
2
- CK
Column Address to Column Address Delay tCCD
1
-
1
-
1
-
1
- CK
Row Precharge Time
4
-
4
- CK
tRP
5
-
5
-
3
-
3
- CK 1
Last Data-In to Precharge Delay Time
(Write Recovery Time : tWR)
tDPL
3
-
3
-
2
-
2
- CK
Last Data-In to Read Command
tDRL
2
-
2
-
2
-
2
- CK
Auto Precharge Write Recovery +
Precharge Time
tDAL
8
-
8
-
6
-
6
- CK
System Clock Cycle Time
CL = 4
4
6
4.5
6
-
-
-
- ns
tCK
CL = 3
5
10
5
10
5
10
5.5
10 ns
Clock High Level Width
tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Clock Low Level Width
tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Data-Out edge to Clock edge Skew
tAC -0.9 0.9 -0.9 0.9 -0.9 0.9 -0.9 0.9 ns
DQS-Out edge to Clock edge Skew
tDQSCK -0.7 0.7 -0.7 0.7 -0.7 0.7 -0.7 0.7 ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
-
0.4
-
0.4
-
0.4 ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns 2,7
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns 2,6
Data Hold Skew Factor
tQHS
-
0.6
-
0.6
-
0.45
-
0.45 ns 7
Input Setup Time
tIS
1.0
-
1.0
-
1.0
-
1.0
- ns 3
Input Hold Time
tIH
1.0
-
1.0
-
1.0
-
1.0
- ns 3
Rev. 1.2/Oct. 02
24