HY5DV641622AT Datasheet, PDF (24/27 Pages) Hynix Semiconductor – 64M(4Mx16) DDR SDRAM

HY5DV641622AT
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
33
Symbol
Min Max
36
Min Max
4
Min Max
5
Min Max
Unit Note
Row Cycle Time
tRC
52.8
-
54
-
56
-
60
- ns
Auto Refresh Row Cycle Time
tRFC
72
-
72
-
72
-
75
- ns
Row Active Time
tRAS
36.3 120K 36 120K 36 120K 40 120K ns
Row Address to Column Address Delay tRCD
6
-
6
-
5
-
4
- CK
Row Active to Row Active Delay
tRRD
2
-
2
-
2
-
2
- CK
Column Address to Column Address
Delay
tCCD
1
-
1
-
1
-
1
- CK
Row Precharge Time
tRP
5
-
5
-
5
-
4
- CK
Last Data-In to Precharge Delay Time
(Write Recovery Time : tWR)
tDPL
3
-
3
-
2
-
2
- CK
Last Data-In to Read Command
tDRL
2
-
2
-
2
-
1
- CK
Auto Precharge Write Recovery +
Precharge Time
tDAL
8
-
8
-
7
-
6
- CK
System Clock Cycle Time
CL = 4.0 tCK
CL = 3.0 tCK
3.3 4.0 3.6 4.0
-
-
-
- ns
-
-
-
-
4
6.5
5
6.5 ns
Clock High Level Width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Clock Low Level Width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Data-Out edge to Clock edge Skew
tAC
-1.0 0.5 -1.0 0.5 -1.0 0.5 -1.0 0.5 ns
DQS-Out edge to Clock edge Skew
tDQSCK -1.0 0.5 -1.0 0.5 -1.0 0.5 -1.0 0.5 ns
DQS-Out edge to Data-Out edge Skew tDQSQ
-
0.4
-
0.4
-
0.4
-
0.4 ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns 1, 6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns 1, 5
Data Hold Skew Factor
tQHS
-
0.4
-
0.4
-
0.4
-
0.75 ns 6
Input Setup Time
tIS
0.9
-
0.9
-
0.9
-
0.9
- ns 2
Input Hold Time
tIH
0.9
-
0.9
-
0.9
-
0.9
- ns 2
Write DQS High Level Width
tDQSH
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK
Write DQS Low Level Width
tDQSL
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK
Clock to First Rising edge of DQS-In tDQSS
0.8 1.25 0.8 1.25 0.8 1.25 0.75 1.25 CK
Rev. 0.7/May. 02
24