HY5DV641622AT Datasheet, PDF (2/27 Pages) Hynix Semiconductor – 64M(4Mx16) DDR SDRAM

HY5DV641622AT
Revision History
4. Revision 0.7 (May. 02)
1) Input leakage current changed from +/-5uA to +/-2uA
3. Revision 0.6 (Dec. 01)
1) Separated ‘Function description’ and ‘Timing diagram’ parts
- These are available in Web site (www.hynix.com)
2. Revision 0.5 (Nov. 01)
1) Changed tCK maximum value
a) 300/275Mhz : Changed from 4.5ns to 4.0ns
b) 250/200Mhz : Changed from 8.0ns to 6.5ns
2) Changed ‘VDDQ range’ from +/- 0.2V to +/- 5%
- Changed from 2.3V/2.5V/2.7V to 2.375V/2.5V/2.625V (min/typ/max)
1. Revision 0.4 (Sep. 01)
1) Removed 183/166Mhz parts from speed bin
2) Changed Cas Latency from 3 to 4 at 300/275Mhz
3) Changed tRCD from 5clk to 6clk at 300/275Mhz
4) Changed tCK maximum value from 8ns to 4.5ns at 300/275Mhz
5) Changed VDD value
a) 275Mhz : Changed from 3.15V/3.30V/3.45V to 3.20V/3.30V/3.45V (min/typ/max)
b) 300Mhz : Changed from 3.15V/3.30V/3.45V to 3.35V/3.45V/3.55V (min/typ/max)
6) Modified ‘Burst Read followed by Burst Write’ function
- Burst Write command must be issued after (CL + BL/2 + 1) ticks of clock from Burst Read command,
not (CL + BL/2) ticks of clock at 300/275Mhz
Rev. 0.7/May. 02
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