HY5DU561622FLTP-5I Datasheet, PDF (24/28 Pages) Hynix Semiconductor – 256M(16Mx16) DDR SDRAM

1HY5DU561622FTP-5I
HY5DU561622FTP-4I
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
Row Cycle Time
(Manual Precharge)
Row Cycle Time
(Auto Precharge)
Auto Refresh Row Cycle Time
Row Active Time
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Last Data-In to Precharge Delay
(Write Recovery Time : tWR)
Last Data-In to Read Command
Auto Precharge Write Recovery + Precharge
Time
System Clock Cycle Time
CL = 4.0
CL = 3.0
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
tRC
tRC_APCG
tRFC
tRAS
tRCDRD
tRCDWT
tRRD
tCCD
tRP
tDPL
tDRL
tDAL
tCK
tCH
tCL
tAC
tDQSCK
tDQSQ
Data-Out hold time from DQS
tQH
Clock Half Period
Data Hold Skew Factor
Input Setup Time
Input Hold Time
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
tHP
tQHS
tIS
tIH
tDQSH
tDQSL
tDQSS
tDS
4
Min
Max
15
-
5
Min
Max
12
-
17
-
14
-
18
-
14
-
40
70K
40
70K
5
-
4
-
2
-
2
-
2
-
2
-
1
-
1
-
5
-
4
-
4
-
3
-
2
-
2
-
9
-
7
-
4.0
7.0
-
-
-
-
5.0
7.0
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
-0.7
0.7
-0.7
0.7
-0.7
0.7
-0.7
0.7
-
0.4
-
0.45
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tCH/L
min
-
tCH/L
min
-
-
0.4
-
0.5
0.75
-
0.75
-
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.85
1.15
0.75
1.25
0.4
-
0.4
-
Unit
Note
CK
CK
CK
ns
CK
CK
CK
CK
CK
CK
CK
CK
ns
ns
CK
CK
ns
ns
ns
ns 1, 6
ns 1, 5
ns
6
ns
2
ns
2
CK
CK
CK
ns
3
Rev. 1.1 / Mar. 2008
24