HY5S5B6ELF-HE Datasheet, PDF (23/27 Pages) Hynix Semiconductor – 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O

1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System Clock
Cycle Time
CAS Latency=3
CAS Latency=2
Clock High Pulse Width
Clock Low Pulse Width
Access Time From Clock
CAS Latency=3
CAS Latency=2
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in
High-Z Time
CAS Latency=3
CAS Latency=2
Symbol
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
H
Min Max
7.5 1000
12 1000
3.0
-
3.0
-
-
6.5
-
9.0
2.0
-
2.0
-
1.0
-
2.0
-
1.0
-
2.0
-
1.0
-
2.0
-
1.0
-
1.0
-
6.5
9.0
S
Min Max
Unit Note
9.5 1000 ns
15 1000 ns
3.5
-
ns 1
3.5
-
ns 1
-
7.0 ns 2
-
10 ns 2
2.0
-
ns
3.0
-
ns 1
1.5
-
ns 1
3.0
-
ns 1
1.5
-
ns 1
3.0
-
ns 1
1.5
-
ns 1
3.0
-
ns 1
1.5
-
ns 1
1.0
-
ns
7.0 ns
10 ns
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev 1.0 / Jul. 2005
23