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HY5S5B6ELF-HE Datasheet, PDF (15/27 Pages) Hynix Semiconductor – 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
CURRENT STATE TRUTH TABLE (Sheet 4 of 4)
Current
State
Command
CS RAS CAS WE
BA0/
BA1
A11-A0
Description
Action
Write
Recovering
H
X
X
X
X
X
Device Deselect
No Operation:
Row Active after tDPL
LL L L
OP CODE
Mode Register Set ILLEGAL
LL L H X
X
Auto or Self Refresh ILLEGAL
L L H L BA
X
Precharge
Write
L L H H BA
Row Add. Bank Activate
Recovering
with Auto L H L L BA Col Add. A10 Write/WriteAP
Precharge L H L H BA Col Add. A10 Read/ReadAP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
LHH H X
X
No Operation
No Operation:
Precharge after tDPL
HX X X X
X
Device Deselect
No Operation:
Precharge after tDPL
LL L L
OP CODE
Mode Register Set ILLEGAL
LL L H X
X
Auto or Self Refresh ILLEGAL
L L H L BA
X
Precharge
ILLEGAL
L L H H BA
Row Add. Bank Activate
ILLEGAL
Refreshing L H L L BA Col Add. A10 Write/WriteAP
L H L H BA Col Add. A10 Read/ReadAP
ILLEGAL
ILLEGAL
LHH H X
X
No Operation
No Operation:
idle after tRC
HX X X X
X
Device Deselect
No Operation:
idle after tRC
LL L L
OP CODE
Mode Register Set ILLEGAL
LL L H X
X
Auto or Self Refresh ILLEGAL
L L H L BA
X
Precharge
ILLEGAL
L L H H BA
Row Add. Bank Activate
Mode
Register L H L L BA Col Add. A10 Write/WriteAP
Accessing L H L H BA Col Add. A10 Read/ReadAP
ILLEGAL
ILLEGAL
ILLEGAL
LHH H X
X
No Operation
No Operation:
idle after 2 clock cycles
HX X X X
X
Device Deselect
No Operation:
idle after 2 clock cycles
Notes
13,14
13
4,13
4,12
4,12
4,9,12
13,14
13
13
13
13
13
13,14
13
13
13
13
13
Rev 1.0 / Jul. 2005
15