HY5S5B6ELF-HE Datasheet, PDF (2/27 Pages) Hynix Semiconductor – 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O

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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
DESCRIPTION
The Hynix Low Power SDRAM(Mobile SDR) is suited for non-PC application which use the batteries such as PDAs, 2.5G
and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix HY5S5B6ELF(P) is a 268,435,456bit CMOS Synchronous Dynamic Random Access Memory. It is organized
as 4banks of 4,194,304x16.
The Low Power SDRAM(Mobile SDR) provides for programmable options including CAS latency of 1, 2, or 3, READ or
WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low
Power SDRAM(Mobile SDR) also provides for special programmable options including Partial Array Self Refresh of a
quarter bank, a half bank, 1bank, 2banks, or all banks.
The Hynix HY5S5B6ELF(P) has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh)
to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automati-
cally adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write cycles in
progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or
Write command on any cycle(This pipelined design is not restricted by a 2N rule).
Deep Power Down Mode is a additional operating mode for Low Power SDRAM(Mobile SDR). This mode can achieve
maximum power reduction by removing power to the memory array within each SDRAM. By using this feature, the sys-
tem can cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-
line layout flexibility.
FEATURES
Standard SDRAM Protocol
● Internal 4bank operation
● Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Low Power Features
- PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- Deep Power Down Mode
● Programmable CAS latency of 1, 2 or 3
● -25^oC ~ 85^oC Operation
● Package Type
: 54ball, 0.8mm pitch FBGA (Lead Free, Lead)
- HY5S5B6ELFP : Lead Free
- HY5S5B6ELF : Lead
256M SDRAM ORDERING INFORMATION
Part Number
HY5S5B6ELF-HE
HY5S5B6ELF-SE
HY5S5B6ELFP-HE
HY5S5B6ELFP-SE
Clock Frequency
133MHz
105MHz
133MHz
105MHz
CAS Latency
3
3
3
3
Organization Interface 54Ball FBGA
4banks x 4Mb x 16 LVCMOS
Lead
Lead Free
Rev 1.0 / Jul. 2005
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