HY5W2B6DLF-HE Datasheet, PDF (22/26 Pages) Hynix Semiconductor – 4Banks x 2M x 16bits Synchronous DRAM

HY5W2B6DLF(P) Series
4Banks x 2M x 16bits Synchronous DRAM
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System Clock
Cycle Time
CAS Latency=3
CAS Latency=2
Clock High Pulse Width
Clock Low Pulse Width
Access Time
From Clock
CAS Latency=3
CAS Latency=2
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in
High-Z Time
CAS Latency=3
CAS Latency=2
Symbol
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
H
Min
Max
7.5
1000
9.5
2.5
-
2.5
-
-
5.4
-
7
2.0
-
2.0
-
1.0
-
2.0
-
1.0
-
2.0
-
1.0
-
2.0
-
1.0
-
1.0
-
5.4
7.0
Unit Note
ns
ns
ns
1
ns
1
ns
2
ns
ns
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
ns
ns
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev. 0.2 / May. 2004
22