HY5W2B6DLF-HE Datasheet, PDF (2/26 Pages) Hynix Semiconductor – 4Banks x 2M x 16bits Synchronous DRAM

HY5W2B6DLF(P) Series
4Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix Mobile SDR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular
phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix HY5W2B6DLF(P) is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It is organized
as 4banks of 2,097,152x16.
The Mobile SDR provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of
1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Mobile SDR also provides for
special programmable options including Partial Array Self Refresh of a quarter bank, a half bank, 1bank, 2banks, or all
banks.
The Hynix HY5W2B6DLF(P) has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh)
to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automati-
cally adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write cycles in
progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or
Write command on any cycle(This pipelined design is not restricted by a 2N rule).
Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power re-
duction by removing power to the memory array within each SDR. By using this feature, the system can cut off alomost
all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility.
FEATURES
● Standard SDR Protocol
● Internal 4bank operation
● Operation Voltage :2.5V Operation
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Low Power Features
- PASR(Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- Deep Power Down Mode
● Programmable CAS latency of 1, 2 or 3
● Package : 54 Ball FBGA (Lead, Lead Free)
- HY5W2B6DLF Seriese : Lead
- HY5W2B6DLFP Seriese : Lead Free
ORDERING INFORMATION
Part Number
HY5W2B6DLF(P)-HE
Clock Frequency
133MHz
CAS
Latency
3
Organization
4banks x 2Mb x 16
Interface
LVCMOS
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.2 / May. 2004
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