HY5DW283222BF Datasheet, PDF (22/30 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

1HY5DW283222BF(P)
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Sym
bol
Test Condition
Speed
2 22 25 28 33 36 4
Unit Note
5
Operating Current
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min);
IDD0
DQ,DM and DQS inputs
changing twice per clock cycle;
350 320 290 260 240 230 220 220 mA
1
address and control inputs
changing once per clock cycle
Operating Current
IDD1
Burst length=2, One bank active
tRC ≥ tRC(min), IOL=0mA
360 330 300 270 250 240 230 220 mA
1
Precharge Standby
Current in Power
Down Mode
IDD2P CKE ≤ VIL(max), tCK=min
90 70 50 50 50 50 50 50 mA
Precharge Standby
CKE ≥ VIH(min), /CS ≥ VIH(min),
Current in Non Power IDD2N tCK = min, Input signals are 310 280 250 220 200 190 180 180 mA
Down Mode
changed one time during 2clks
Active Standby Cur-
rent in Power Down
Mode
IDD3P CKE ≤ VIL(max), tCK=min
90 70 50 50 50 50 50 50 mA
Active Standby Cur-
rent in Non Power
Down Mode
CKE ≥ VIH(min), /CS ≥ VIH(min),
IDD3N tCK=min, Input signals are
360 330 300 290 250 240 230 220 mA
changed one time during 2clks
Burst Mode Operat-
ing Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
700 650 600 550 500 450 450 450 mA 1
Auto Refresh Current
IDD5
tRC ≥ tRFC(min),
All banks active
400 400 350 350 300 300 270 270 mA 1,2
Self Refresh Current IDD6 ^{CKE ≤ 0.2V}
4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 mA
Operating Current -
Four Bank Operation
Four bank interleaving with
IDD7 BL=4, Refer to the following
page for detailed test condition
900 800 700 600 500 400 400 400 mA
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 1.1 / May. 2005
22