HY5DW283222BF Datasheet, PDF (16/30 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

Power-Up Sequence
1HY5DW283222BF(P)
VDD
VDDQ
VTT
VREF
/CLK
CLK
tVTD
CKE
CMD
LVCMOS Low Level
tIS tIH
NOP
PRE
EMRS
MRS
NOP
PRE
AREF
MRS
ACT
RD
DM
ADDR
CODE
CODE
CODE
CODE
CODE
A10
CODE
CODE
CODE
CODE
CODE
BA0, BA1
DQS
DQ'S
CODE
CODE
CODE
CODE
CODE
T=200usec
Power UP
VDD and CK stable
tRP
tMRD
Precharge All
EMRS Set
MRS Set
Reset DLL
(with A8=H)
tMRD
tRP
tRFC
tMRD
tXSRD*
Precharge All 2 or more
MRS Set
Auto Refresh ^{(with A8=L)}
Non-Read
Command
READ
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
Rev. 1.1 / May. 2005
16