HY5PS12421AFP Datasheet, PDF (21/37 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

512Mb A-ver. DDR2 SDRAM
Parameter
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Symbol
tWR
tDAL
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
t_CKE
t_AOND
t_AON
t_AONPD
t_AOFD
t_AOF
t_AOFPD
tANPD
tAXPD
tOIT
tDelay
DDR2-533
min
max
15
-
WR+tRP
-
7.5
-
7.5
tRFC + 10
200
-
2
-
2
6 - AL
DDR2-400
min
max
15
-
WR+tRP
-
10
-
7.5
tRFC + 10
200
-
2
-
2
6 - AL
-Continue-
Unit Note
ns
tCK
14
ns
24
ns
3
ns
tCK
tCK
tCK
1
tCK
1, 2
3
3
tCK
27
2
2
2
2
tCK
tAC(min)
tAC(max)+
1
tAC(min)
tAC(max)+
1
ns
16
2tCK+
2tCK+
tAC(min)+2 tAC(max)+ tAC(min)+2 tAC(max)+
ns
1
1
2.5
2.5
2.5
2.5
tCK
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+
0.6
ns
17
2.5tCK+
2.5tCK+
tAC(min)+2 tAC(max)+ tAC(min)+2 tAC(max)+
ns
1
1
3
3
tCK
8
8
tCK
0
12
0
12
ns
tIS+tCK+tIH
tIS+tCK+tIH
ns
15
Rev. 0.2 / Mar. 2005
21