HY5PS12421AFP Datasheet, PDF (18/37 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

512Mb A-ver. DDR2 SDRAM
For purposes of IDD testing, the following parameters are to be utilized
Speed
Bin
(CL-tRCD-tRP)
CL(IDD)
tRCD(IDD)
tRC(IDD)
tRRD(IDD)-x4/x8
tRRD(IDD)-x16
tCK(IDD)
tRASmin(IDD)
tRASmax(IDD)
tRP(IDD)
tRFC(IDD)-256Mb
tRFC(IDD)-512Mb
tRFC(IDD)-1Gb
DDR2-800
5-5-5
5
12.5
6-6-6
6
15
57.25
60
7.5
10
2.5
45
70000
12.5
75
105
127.5
7.5
10
2.5
45
70000
15
75
105
127.5
DDR2-667
4-4-4
4
12
5-5-5
5
15
57
60
7.5
10
3
45
70000
12
75
105
127.5
7.5
10
3
45
70000
15
75
105
127.5
DDR2-533
3-3-3
3
11.25
4-4-4
4
15
56.25
60
7.5
10
3.75
45
70000
11.25
75
105
127.5
7.5
10
3.75
45
70000
15
75
105
127.5
DDR2-400
3-3-3
3
15
55
7.5
10
5
40
70000
15
75
105
127.5
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum ^tRC(IDD) without violating ^tRRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
-DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)
-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
Rev. 0.2 / Mar. 2005
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