HY62V8200B Datasheet, PDF (2/12 Pages) Hynix Semiconductor – HY62V8200B Series 256Kx8bit CMOS SRAM

Y62V8200B Series
DESCRIPTION
FEATURES
The HY62V8200B is a high speed, low power and
2M bit CMOS SRAM organized as 262,144 words
by 8bit. The HY62V8200B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particularly well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup( LL-part )
-. 2.0V(min) data retention
Standard pin configuration
-. 32-sTSOPI-8X13.4, 32-TSOPI -8X20
(Standard and Reversed)
Product
Voltage Speed
Operation
No.
(V)
(ns)
Current/Icc(mA)
HY62V8200B 3.0~3.6 70/85/100
5
HY62V8200B-E 3.0~3.6 70/85/100
5
HY62V8200B-I 3.0~3.6 70/85/100
5
Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
Standby
Current(uA)
25
25
25
Temperature
(°C)
0~70
-25~85(E)
-40~85(I)
PIN CONNECTION
A11 1
A9
A8
2
3
A13 4
/WE
CS2
5
6
A15 7
Vcc 8
A17 9
A16 10
A14 11
A12 12
A7
A6
13
14
A5 15
A4 16
32 /OE A11 1
31
30
A10 A9
/CS1 A8
2
3
29 DQ8 A13 4
28
27
DQ7 /WE
DQ6 CS2
5
6
26 DQ5 A15 7
25 DQ4 Vcc 8
24 Vss A17 9
23 DQ3 A16 10
22 DQ2 A14 11
21 DQ1 A12 12
20
19
A0
A1
A7
A6
13
14
18 A2 A5 15
17 A3 A4 16
32 /OE
31
30
A10
/CS1
29 DQ8
28
27
DQ7
DQ6
26 DQ5
25 DQ4
24 Vss
23 DQ3
22 DQ2
21 DQ1
20
19
A0
A1
18 A2
17 A3
TSOP-I
(Standard)
sTSOP-I
(Standard)
PIN DESCRIPTION
BLOCK DIAGRAM
Pin Name
Pin Function
A0
/CS1
Chip Select 1
CS2
Chip Select 2
/WE
Write Enable
/OE
Output Enable
A0 ~ A17
Address Input
I/O1 ~ I/O8
Data Input/Output
Vcc
Power(3.0V~3.6V)
Vss
Ground
A17
ROW
DECODER
MEMORY ARRAY
256K x 8
I/O1
I/O8
/CS1
CS2
/WE
/OE
Rev 06 / Apr. 2001
2