HYMD232646B8J-J Datasheet, PDF (17/18 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD232646B8J
SERIAL PRESENCE DETECT
Bin Sort : J(DDR333@CL=2.5), D4/D43(DDR400@CL=3)
Byte#
Function Description
Function Supported
D43
D4
J
0 Number of Bytes written into serial memory at module manufacturer
128 Bytes
1 Total number of Bytes in SPD device
256 Bytes
2 Fundamental memory type
DDR SDRAM
3 Number of row address on this assembly
13
4 Number of column address on this assembly
10
5 Number of physical banks on DIMM
1Bank
6 Module data width
64 Bits
7 Module data width (continued)
-
8 Module voltage Interface levels(VDDQ)
SSTL 2.5V
9
DDR SDRAM cycle time at CAS Latency=2.5(tCK)@DDR333,
3(tCK)@DDR400
5.0ns 5.0ns 6.0ns
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
+/-0.7ns
11 Module configuration type
Non-ECC
12 Refresh rate and type
7.8us & Self refresh
13 Primary DDR SDRAM width
x8
14 Error checking DDR SDRAM data width
N/A
15
Minimum clock delay for back-to-back random column
address(tCCD)
1 CLK
16 Burst lengths supported
2,4,8
17 Number of banks on each DDR SDRAM
4 Banks
18 CAS latency supported
2, 2.5, 3 2, 2.5, 3 2, 2.5
19 CS latency
0
20 WE latency
1
21 DDR SDRAM module attributes
Differential Clock Input
22 DDR SDRAM device attributes : General
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
23 DDR SDRAM cycle time at CL=2.0(tCK), 2.5(tCK)
6ns
6ns
7.5ns
24 DDR SDRAM access time from clock at CL=2.0(tAC), 2.5(tAC)
+/-0.7ns +/-0.7ns +/-0.7ns
25 DDR SDRAM cycle time at CL=1.5(tCK), 2.0(tCK)
7.5ns 7.5ns
-
26 DDR SDRAM access time from clock at CL=1.5(tAC), 2.0(tAC)
+/-0.75ns +/-0.75ns
-
27 Minimum row precharge time(tRP)
15ns
18ns
18ns
28 Minimum row activate to row active delay(tRRD)
10ns
10ns
12ns
29 Minimum RAS to CAS delay(tRCD)
15ns
18ns
18ns
30 Minimum active to precharge time(tRAS)
40ns
40n
42ns
31 Module row density
256MB
32 Command and address signal input setup time(tIS)
0.6ns 0.6ns 0.75ns
33 Command and address signal input hold time(tIH)
0.6ns 0.6ns 0.75ns
34 Data signal input setup time(tDS)
0.4ns 0.4ns 0.45ns
35 Data signal input hold time(tDH)
0.4ns 0.4ns 0.45ns
36~40 Reserved for VCSDRAM
Undefined
41 Minimum active / auto-refresh time ( tRC)
55ns
58ns
60ns
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
70ns
70ns
72ns
43 Maximum cycle time (tCK max)
10ns
10ns
12ns
44 Maximim DQS-DQ skew time(tDQSQ)
0.4ns 0.4ns 0.45ns
45 Maximum read data hold skew factor(tQHS)
0.50ns 0.50ns 0.55ns
46~61 Superset information(Reserved for IDD values, Tcase, etc.)
Undefined
62 SPD Revision code
Initial release
63 Checksum for Bytes 0~62
-
64 Manufacturer JEDEC ID Code
Hynix JEDEC ID
65~71 --------- Manufacturer JEDEC ID Code
-
Hexa Value
D43
D4
J
80h
08h
07h
0Dh
0Ah
01h
40h
00h
04h
50h
50h
60h
70h
00h
82h
08h
00h
01h
0Eh
04h
1Ch
1Ch
0Ch
01h
02h
20h
C0h
60h
60h
75h
70h
70h
70h
75h
75h
00h
75h
75h
00h
3Ch
48h
48h
28h
28h
30h
3Ch
48h
48h
28h
28h
2Ah
40h
60h
60h
75h
60h
60h
75h
40h
40h
45h
40h
40h
45h
00h
37h
3Ah
3Ch
46h
46h
48h
28h
28h
30h
28h
28h
2Dh
50h
50h
55h
00h
00h
66h
81h
00h
ADh
00h
Note
1
1
2
2
2
2
2
2
Rev. 0.2 / Apr. 2003
17