HYMD232646B8J-J Datasheet, PDF (1/18 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

DESCRIPTION
32Mx64 bits
Unbuffered DDR SDRAM DIMM
HYMD232646B8J
Hynix HYMD232646B8J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Mod-
ules(DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD232646B8J series consists of
eight 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.Hynix HYMD232646B8J
series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy
interchange and addition.
Hynix HYMD232646B8J series is designed for high speed of up to 200MHz and offers fully synchronous operations
referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD232646B8J series incorporates SPD(serial presence detect). Serial presence detect function is imple-
mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 256MB (32M x 64) Unbuffered DDR DIMM based on • Data(DQ), Data strobes and Write masks latched on
32Mx8 DDR SDRAM
both rising and falling edges of the clock
• JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
• Data inputs on DQS centers when write (centered
DQ)
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• 2.6V +/- 0.1V VDD and VDDQ Power supply for
DDR400
• Data strobes synchronized with output data for read
and input data for write
• Programmable CAS Latency 3/ 2 / 2.5 supported
• All inputs and outputs are compatible with SSTL_2
interface
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Fully differential clock operations (CK & /CK) with
• tRAS Lock-out function supported
125MHz/133MHz/166MHz/200MHz
• Internal four bank operations with single pulsed RAS
•
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
•
Auto refresh and self refresh supported
of the clock
• 8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD232646B8J-J
HYMD232646B8J-D4
HYMD232646B8J-D43
Power Supply
VDD=VDDQ=2.5V
VDD=VDDQ=2.6V
VDD=VDDQ=2.6V
Clock Frequency Interface
166MHz (DDR333)
SSTL_2
200MHz (DDR400)
SSTL_2
200MHz (DDR400)
SSTL_2
Form Factor
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Apr. 2003
1