HY5PS1G431ALFP Datasheet, PDF (17/36 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM

HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
Conditions
Units
Operating one bank active-precharge current; ^tCK = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRAS} = ^tRAS
IDD0 min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCH-
mA
ING;Data bus inputs are SWITCHING
IDD1
Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
tCK ₌ tCK(IDD), tRC ₌ tRC _(IDD), tRAS ₌ tRASmin(IDD), tRCD ₌ tRCD(IDD) _{; CKE is HIGH, CS is HIGH mA}
between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
IDD2P ^{Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and} mA
address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2Q ^{Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other}
mA
control and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2N ^{Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control} mA
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current; All banks open; ^tCK = ^tCK(IDD); _{Fast PDN Exit MRS(12) = 0}
mA
IDD3P CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Slow PDN Exit MRS(12) = 1
mA
IDD3N
Active standby current; All banks open; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} =tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH- mA
ING; Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL
IDD4W = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid mA
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL =
IDD4R CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH
mA
between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
Burst refresh current; ^tCK = ^tCK(IDD); Refresh command at every ^tRFC(IDD) interval; CKE is HIGH,
IDD5B CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus _mA
inputs are SWITCHING
IDD6
Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are FLOAT-
ING; Data bus inputs are FLOATING
mA
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL =
CL(IDD), AL = ^{tRCD(IDD)-1*tCK(IDD); tCK} = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRRD} = ^{tRRD(IDD), tRCD} =
1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during
mA
DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
Rev. 0.7 / Oct. 2007
17