HY5DU281622ET Datasheet, PDF (15/34 Pages) Hynix Semiconductor – 128M(8Mx16) GDDR SDRAM

HY5DU281622ET
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is
applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS
LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state,
where they will remain until driven in normal operation (by a read access). After all power supply and reference volt-
ages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable com-
mand.
Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Reg-
ister set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting
the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-
MOS low state. (All the other input pins may be undefined.)
No power sequencing is specified during power up or power down given the following cirteria :
• VDD and VDDQ are driven from a single power converter output.
• VTT is limited to 1.4025V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation).
• VREF tracks VDDQ/2.
• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-
ship must be adhered to during power up :
Voltage description
Sequencing
Voltage relationship to avoid latch-up
VDDQ
After or with VDD
< VDD + 0.3V
VTT
After or with VDDQ
< VDDQ + 0.3V
VREF
After or with VDDQ
< VDDQ + 0.3V
2. Start clock and maintain stable clock for a minimum of 200µsec.
3. After stable power and clock, apply NOP or DESELECT conditionS and take CKE high.
4. Following the NOP command, a PRECHARGE ALL command should be applied
5. Issue Extended Mode Register Set (EMRS) to enable DLL.
6. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200
cycles(tXSRD) of clock are required for locking DLL)
7. Issue Precharge commands for all banks of the device.
8. Issue 2 or more Auto Refresh commands.
Rev. 0.5 / Jan. 2005
15