HYMD532646CP6-H Datasheet, PDF (13/30 Pages) Hynix Semiconductor – 184pin Unbuffered DDR SDRAM DIMMs

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184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
1GB, 128M x 64 Unbuffered DIMM: HYMD512646CP8[J]
Symbol
Test Condition
Speed
Unit
DDR400B DDR333 DDR266B
Note
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
clock cycle
1520
1440
1280
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control inputs
changing once per clock cycle
1840
1680
1440
mA
IDD2P All banks idle; Power down mode; CKE=Low, tCK=tCK(min)
160
mA
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
IDD2F address and control inputs changing once per clock cycle.
560
mA
VIN=VREF for DQ, DQS and DM
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
720
mA
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
IDD3N
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
960
mA
inputs changing once per clock cycle
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
2160
2000
1840
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
2320
2160
1920
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for
DDR266A & DDR266B at 133Mhz; distributed refresh
2560
2400
2240
mA
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
80
mA
48
mA
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
3360
3280
3200
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 / Feb. 2006
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