HYMD532646CP6-H Datasheet, PDF (12/30 Pages) Hynix Semiconductor – 184pin Unbuffered DDR SDRAM DIMMs

11
184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
512MB, 64M x 72 ECC Unbuffered DIMM: HYMD564726CP8[J]
Symbol
Test Condition
Speed
Unit
DDR400B DDR333 DDR266B
One bank; Active - Precharge; tRC=tRC(min);
IDD0
tCK=tCK(min); DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
1170
1080
900
mA
clock cycle
One bank; Active - Read - Precharge; Burst Length=2;
IDD1 tRC=tRC(min); tCK=tCK(min); address and control inputs
1530
1350
1080
mA
changing once per clock cycle
IDD2P All banks idle; Power down mode; CKE=Low, tCK=tCK(min)
90
mA
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
IDD2F address and control inputs changing once per clock cycle.
315
mA
VIN=VREF for DQ, DQS and DM
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
405
mA
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
IDD3N
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
540
mA
inputs changing once per clock cycle
Burst=2; Reads; Continuous burst; One bank active;
IDD4R Address and control inputs changing once per clock cycle;
1890
1710
1530
mA
tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
IDD4W
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
2070
1890
1620
mA
clock cycle
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for
DDR266A & DDR266B at 133Mhz; distributed refresh
2340
2160
1980
mA
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
45
mA
27
mA
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
3240
3150
3060
mA
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 / Feb. 2006
12