HYMD532646CP6-H Datasheet, PDF (11/30 Pages) Hynix Semiconductor – 184pin Unbuffered DDR SDRAM DIMMs

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184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
512MB, 64M x 64 Unbuffered DIMM: HYMD564646CP8[J]
Symbol
Test Condition
Speed
Unit
DDR400B DDR333 DDR266B
One bank; Active - Precharge; tRC=tRC(min);
IDD0
tCK=tCK(min); DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
1040
960
clock cycle
800
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control inputs
changing once per clock cycle
1360
1200
960
mA
IDD2P All banks idle; Power down mode; CKE=Low, tCK=tCK(min)
80
mA
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
IDD2F address and control inputs changing once per clock cycle.
280
mA
VIN=VREF for DQ, DQS and DM
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
360
mA
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
IDD3N
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
480
mA
inputs changing once per clock cycle
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
1680
1520
1360
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
1840
1680
1440
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for
DDR266A & DDR266B at 133Mhz; distributed refresh
2080
1920
1760
mA
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
40
mA
24
mA
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
2880
2800
2720
mA
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 / Feb. 2006
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