HYMD116645B8-M Datasheet, PDF (10/17 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD116645B(L)8-M/K/H/L
-Continued -
Parameter
DDR266(2-2-2) DDR266A
Symbol
Min Max Min Max
Input Setup Time (fast slew rate) tIS
0.9
-
0.9
-
Input Hold Time (fast slew rate) tIH
0.9
-
0.9
-
Input Setup Time
(slow slew rate)
tIS
1.0
-
1.0
-
Input Hold Time (slow slew rate) tIH
1.0
-
1.0
-
Input Pulse Width
tIPW
2.2
2.2
Write DQS High Level Width
tDQSH 0.35
-
0.35
-
Write DQS Low Level Width
tDQSL 0.35
-
0.35
-
Clock to First Rising edge of
DQS-In
tDQSS 0.72 1.28 0.75 1.25
Data-In Setup Time to DQS-In
(DQ & DM)
tDS
0.5
-
0.5
-
Data-in Hold Time to DQS-In
(DQ & DM)
tDH
0.5
-
0.5
-
DQ & DM Input Pulse Width
tDIPW 1.75
-
1.75
-
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9 1.1
Read DQS Postamble Time
tRPST
0.4
0.6
0.4 0.6
Write DQS Preamble Setup Time tWPRES
0
-
0
-
Write DQS Preamble Hold Time tWPREH 0.25
-
0.25
-
Write DQS Postamble Time
tWPST
0.4
0.6
0.4 0.6
Mode Register Set Delay
tMRD
2
-
2
-
Exit Self Refresh to Any Execute
Command
tXSC
200
-
200
-
Average Periodic Refresh Interval tREFI
-
15.6
-
15.6
DDR266B
Min Max
0.9
-
0.9
-
DDR200
Unit
Min Max
Note
1.1
-
ns 2,3,5,6
1.1
-
ns 2,3,5,6
1.0
-
1.1
-
ns 2,4,5,6
1.0
-
1.1
-
ns 2,4,5,6
2.2
2.5
-
ns
6
0.35
-
0.35
-
CK
0.35
-
0.35
-
CK
0.75 1.25 0.75 1.25 CK
0.5
-
0.6
-
ns
6,7,
11~13
0.5
-
0.6
-
ns
1.75
-
2
-
ns
0.9 1.1 0.9 1.1 CK
0.4 0.6 0.4 0.6 CK
0
-
0
-
CK
0.25
-
0.25
-
CK
0.4 0.6 0.4 0.6 CK
2
-
2
-
CK
200
-
200
-
CK
8
- 15.6 - 15.6 us
Rev. 0.3/May. 02
10