HCPL-1930 Datasheet, PDF (7/12 Pages) Agilent(Hewlett-Packard) – Dual Channel Line Receiver Dual Channel Line Receiver Dual Channel Line Receiver

7
Typical Specifications
T_A = 25°C, V_CC = 5 V
Parameter
Resistance (Input-Output)
Capacitance (Input-Output)
Input-Input Insulation
Leakage Current
Resistance (Input-Input)
Capacitance (Input-Input)
Propagation Delay Time of Enable
from V to V
EH
EL
Propagation Delay Time of Enable
from V to V
EL
EH
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Input Capacitance
Symbol
R_I-O
C_I-O
I_I-I
Typ.
10¹²
1.7
0.5
R
10¹²
I-I
C
0.55
I-I
t
35
ELH
t
35
EHL
Units
Ω
pF
nA
Ω
pF
ns
Test Conditions
V_I-O = 500 V dc
f = 1 MHz
45% Relative Humidity,
V_I-I = 500 Vdc, t = 5 s
V = 500 Vdc
I-I
f = 1 MHz
R_L = 510 Ω, C_L = 15 pF,
ns
I = 13 mA, V = 3 V, V = 0 V
I
EH
EL
Fig.
Note
3, 13
3, 13
11
11
11
6, 7 3, 7
6, 7 3, 8
t_r
30
ns
3
R_L = 510 Ω, C_L = 15 pF, I_I = 13 mA
t_f
24
ns
3
C_I
60
pF
f = 1 MHz, V_I = 0,
3
PINS 1 to 2 or 5 to 6
Notes:
1. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each isolator. The power supply bus
for the isolators should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to
suppress regenerative feedback via the power supply.
2.
Derate
linearly
at
1.2
mA/°C
above
T
A
=
100°C.
3. Each channel.
4. Device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together.
5. The t propagation delay is measured form the 6.5 mA point on the trailing edge of the input pulse to the 1.5 V point on the trailing
PLH
edge of the output pulse.
6. The t propagation delay is measured from the 6.5 mA point on the leading edge of the input pulse to the 1.5 V point on the leading
PHL
edge of the output pulse.
7. The t enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point
ELH
on the trailing edge of the output pulse.
8. The t enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point
EHL
on the leading edge of the output pulse.
9. CM is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state, i.e.
H
V > 2.0 V.
OUT
10. CM is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state, i.e.
L
V < 0.8 V.
OUT
11. Measured between adjacent input leads shorted together, i.e. between 1, 2 and 4 shorted together and pins 5, 6 and 8 shorted
together.
12. No external pull up is required for a high logic state on the enable input.
13. Measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together.
14. Parameters shall be tested as part of device initial characterization and after process changes. Parameters shall be guaranteed to the
limits specified for all lots not specifically tested.
15. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25, 125, and -55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).