HDMP-1636A Datasheet, PDF (6/18 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet and Fibre Channel SerDes ICs

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HDMP-1636A/1646A/T1636A (Receiver Section) – Gigabit Ethernet
Timing Characteristics
T_A = 0°C to +70°C, V_CC = 3.15 V to 3.45 V
Symbol
Parameter
Units Min.
b_sync^[1,2]
Bit Sync Time
bits
f_lock
Frequency Lock at Powerup
µs
t_{valid_before}
Time Data Valid Before Rising Edge of RBC
nsec
2.5
t_{valid_after}
Time Data Valid After Rising Edge of RBC
nsec
1.5
t_duty
t_A-B[3]
RBC Duty Cycle
Rising Edge Time Difference between
RBC0 and RBC1
%
40
nsec
7.5
t_rxlat^[4]
Receiver Latency
nsec
bits
Typ.
22.4
28.0
Max.
2500
500
60
8.5
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C_PLL = 0.1 µF.
3. Garranteed at room temperature.
4. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
HDMP-1636/1646A/T1636A (Receiver Section) – Fibre Channel
Timing Characteristics
T_A[1] = 0°C to +70°C, V_CC = 3.15 V to 3.45 V
Symbol
Parameter
Units Min.
b_sync^[2,3]
Bit Sync Time
bits
t_{valid_before}
Time Data Valid Before Rising Edge of RBC
nsec
3
t_{valid_after}
Time Data Valid After Rising Edge of RBC
nsec
1.5
t_duty
t_A-B[4]
RBC Duty Cycle
Rising Edge Time Difference between
RBC0 and RBC1.
%
40
nsec
8.9
t_rxlat^[5]
Receiver Latency
nsec
bits
Typ.
9.4
24.5
26
Max.
2500
60
9.9
Notes:
1. Device tested and characterized under T_A conditions specified, with T_C monitored at approximately 20° higher than T_A.
2. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
3. Tested using C_PLL = 0.1 µF.
4. The RBC clock skew is calculated as t_A-B(max) - t_A-B(min).
5. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).