HDMP-1636A Datasheet, PDF (14/18 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet and Fibre Channel SerDes ICs

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TRx I/O Definition
Name
BYTSYNC
-DIN
+DIN
-DOUT
+DOUT
ENBYTSYNC
GND
*GND
GND_RXA
GND_RXTTL
GND_TXA
GND_TXHS
LOOPEN
N/C
RBC1
RBC0
REFCLK
Pin Type
Signal
47 O-TTL Byte Sync Output: An active high output. Used to indicate detection of
a comma character (0011111XXX). It is only active when
ENBYTSYNC is enabled.
52 HS_IN Serial Data Inputs: High-speed inputs. Serial data is accepted from the
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± DIN inputs when LOOPEN is low.
61 HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when
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LOOPEN is set low. When LOOPEN is set high, these outputs are held
static at logic 1.
24 I-TTL Enable Byte Sync Input: When high, turns on the internal byte sync
function to allow clock synchronization to a comma character,
(0011111XXX). When the line is low, the function is disabled and will
not reset registers and clocks, or strobe the BYTSYNC line.
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S Logic Ground: Normally 0 volts. This ground is used for internal PECL
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logic. It should be isolated from the noisy TTL ground as well as possible.
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1
This pin is bonded to an isolated pad and has no functionality. However,
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it is recommended that this pin be connected to GND in order to conform
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with the X3T11 “10-bit specification,” and to help dissipate heat.
51
S Analog Ground: Normally 0 volts. Used to provide a clean ground
plane for the receiver PLL and high-speed analog cells.
32
S TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells
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of the receiver section.
46
15
S Analog Ground: Normally 0 volts. Used to provide a clean ground plane
for the PLL and high-speed analog cells.
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S Ground: Normally 0 volts.
19 I-TTL Loopback Enable Input: When set high, the high-speed serial signal is
internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
± DOUT outputs are held static at logic 1. When set low, ± DOUT outputs
and ± DIN inputs are active.
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This pin is connected to an isolated pad and has no functionality. It can
be left open, however, TTL levels can also be applied to this pin.
30 O-TTL Receiver Byte Clocks: The receiver section recovers two 53.125 MHz
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(Fibre Channel)/62.5 MHz (Gigabit Ethernet) receive byte clocks. These
two clocks are 180 degrees out of phase. The receiver parallel data
outputs are alternately clocked on the rising edge of these clocks.
The rising edge of RBC1 aligns with the output of the comma character
(for byte alignment) when detected.
22 I-TTL Reference Clock and Transmit Byte Clock: A 106.25 MHz (Fibre
Channel)/125 MHz (Gigabit Ethernet) clock supplied by the host system.
The transmitter section accepts this signal as the frequency reference
clock. It is multiplied by 10 to generate the serial bit clock and other
internal clocks. The transmit side also uses this clock as the transmit byte
clock for the incoming parallel data TX[0]..TX[9]. It also serves as the
reference clock for the receive portion of the transceiver.