HMMC-3108 Datasheet, PDF (4/8 Pages) Agilent(Hewlett-Packard) – DC-16 GHz Packaged Divide-by-8

Applications
The HMMC-3108 is designed for
use in high frequency
communications, microwave
instrumentation, and EW radar
systems where low phase–noise
PLL control circuitry or broad–
band frequency translation is
required.
Operation
The device is designed to
operate when driven with either
a single–ended or differential
sinusoidal input signal over a
200 MHz to 16 GHz bandwidth.
Below 200 MHz the prescaler
input is “slew–rate” limited,
requiring fast rising and falling
edge speeds to properly divide.
The device will operate at
frequencies down to dc when
driven with a square–wave.
Due to the presence of an off–
chip RF–bypass capacitor inside
the package (connected to the
V_CC contact on the device), and
the unique design of the device
itself, the component may be
biased from either a single
positive or single negative
supply bias. The backside of the
package is not dc connected to
any dc bias point on the device.
For positive supply operation,
V_CC pins are nominally biased at
any voltage in the +4.5 to +6.5
volt range with pin 8 (V_EE)
grounded. For negative bias
operation V_CC pins are typically
grounded and a negative voltage
between- 4.5 to- 6.5voltsis
applied to pin 8 (V_EE).
ac–Coupling and dc–Blocking
All RF ports are dc connected
on–chip to the V_CC contact
through on–chip 50W resistors.
Under any bias conditions where
V_CC is not dc grounded the RF
ports should be ac coupled via
series capacitors mounted on
the PC– board at each RF port.
Only under bias conditions
where V_CC is dc grounded (as is
typical for negative bias supply
operation) may the RF ports be
direct coupled to adjacent
circuitry or in some cases, such
as level shifting to subsequent
stages. In the latter case the
package heat sink may be
“floated” and bias applied as the
difference between V_CC and V_EE.
Input dc Offset
If an RF signal with sufficient
signal to noise ratio is present at
the RF input lead, the prescaler
will operate and provide a
divided output equal the input
frequency divided by the divide
modulus. Under certain “ideal”
conditions where the input is
well matched at the right input
frequency, the component may
“self–oscillate”, especially under
small signal input powers or
with only noise present at the
input. This “self–oscillation” will
produce an undesired output
signal also known as a false
trigger. To prevent false triggers
or self– oscillation conditions,
apply a 20 to 100 mV dc offset
voltage between the RFi n and
RFi n ports. This prevents noise
or spurious low level signals
from triggering the divider.
Adding a 10KW resistor between
the unused RF input to a contact
point at the VEE potential will
result in an offset of » 25mV
between the RF inputs. Note,
however, that the input
sensitivity will be reduced
slightly due to the presence of
this offset.
V_CC
V_CC
V_CC
6
4
2
150p
Vcc
Vcc
By
poss
50 50
IN ₅
IN
÷
IN
7
IN
Vee
SOIC8 w/Backside GND
8
V_EE
Figure 1. Simplified Schematic
4
Vcc
50
50
OUT
OUT
Vpwr
sel
3 ^OUT
OUT
Pin 1