HPMX-2005 Datasheet, PDF (3/12 Pages) Agilent(Hewlett-Packard) – Silicon Bipolar RFIC 100 MHz Vector Modulator

HPMX-2005 Pin
Descriptions
V_CC (pins 1, 2 & 16)
These three pins provide DC
power to the RFIC, and are con-
nected together internal to the
package. They should be con-
nected to a 5 V supply, with ap-
propriate AC bypassing (1000 pF
typ.) used near the pins, as shown
in figures 1 and 2.The voltage on
these pins should always be
kept at least 0.8 V more posi-
tive than the DC level on any
of pins 5, 6, 11, or 12. Failure to
do so may result in the modulator
drawing sufficient current
through the data or reference in-
puts to damage the IC (see also
Figure 5).
Ground (pins 3, 4, 10, 13 & 14)
These pins should connect with
minimal inductance to a solid
ground plane (usually the back-
side of the PC board). Recom-
mended assembly employs
multiple plated through via holes
where these leads contact the PC
board.
I_ref (pin 12) and Q_ref (pin 5)
I_mod (pin 11) and Q_mod (pin 6)
Inputs
The I and Q inputs are designed
for unbalanced operation but can
be driven differentially with simi-
lar performance. The recom-
mended level of unbalanced I and
V_CC = +5 V
1000 pF
1000 pF
Q signals is 1.5 V_p-p with an aver-
age level of 2.5 V above ground.
The reference pins should be DC
biased to this average data signal
level (V_CC/2 or 2.5 V typ.). For
single ended drive, pins 5 and 12
can be tied together. For differen-
tial operation, 0.75 V_p-p signals
may be applied across the I_mod/I_ref
and the Q_mod/Q_ref pairs. The aver-
age level of all four signals should
be about 2.5 V above ground. The
impedance between I_in or Q_in and
ground is typically 10 kΩ and the
impedance between I_mod and I_ref
or Q_mod and Q_ref is typically
10␣ k Ω. The input bandwidth typi-
cally exceeds 40 MHz. It is pos-
sible to reduce LO leakage
through the IC by applying slight
DC imbalances between I_mod and
I_ref and/or Q_mod and Q_ref (see page
9). All performance data shown
on this data sheet was taken with
unbalanced I/Q inputs.
pins 7 and 8, as shown in figure 2.
The internal phase shifter allows
operation from 25 to 200 MHz (or
to 250 MHz by using pin 9 — see
below). The recommended LO
input level is -12 dBm. All perfor-
mance data shown on this data
sheet was taken with unbalanced
LO operation.
Phase Adjust (pin 9)
Applying a DC bias to this pin al-
ters the frequency range of the in-
ternal RC phase shifter. In normal
operation, this pin is not con-
nected. (Do not ground this pin!)
For operation at LO frequencies
above 140 MHz, superior modula-
tion error can be achieved by con-
necting pin 9 to V_CC (5 V). The
resulting changes in performance
are shown in figures 13 through
18. Use of pin 9 extends the
operating range to beyond
250␣ MHz.
LO Input (pins 7 and 8)
The LO input of the HPMX-2005 is
balanced (differential) and
matched to 50 Ω. For drive from a
unbalanced LO, pin 7 should be
AC coupled to the LO using a 50 Ω
transmission line and a blocking
capacitor (1000 pF typ.), and pin 8
should be AC grounded (1000 pF
capactitor typ.), as shown in fig-
ure 1. For drive from a differential
LO source, 50 Ω transmission
lines and blocking capacitors
(1000 pF typ.) are used on both
RF Output (pin 15)
The RF output of the HPMX-2005
is configured for unbalanced op-
eration, and connects directly to
an emitter follower in the output
stage of the IC. The output imped-
ance is appropriate for connection
without further impedance match-
ing to transmission lines of
characteristic impedance between
50 Ω and 150 Ω. The reflection
coefficients are given in figure 11.
A DC blocking capacitor (1000 pF
typ.) is required on this pin.
V_CC = +5 V
1000 pF
1000 pF
1
2
3
4
Qref
5
Qmod
6
LOin
7
1000 pF
8
1000 pF
16
1000 pF
15
RF _out
14
13
12
11
Imod
10
9
OPTIONAL FOR
OPERATION TO 250 MHz
Figure 1. HPMX-2005 Connections Showing Unbalanced
LO and I/Q Inputs.
7-56
1
16
2
15
3
14
1000 pF
RFout
Qref
Qmod
LO +
1000 pF
LO –
1000 pF
4
13
5
12
6
11
7
10
Iref
Imod
8
9
OPTIONAL FOR
OPERATION TO 250 MHz
Figure 2. HPMX-2005 Connections Showing Differential
LO and I/Q Inputs.