HDMP-0480 Datasheet, PDF (2/11 Pages) Agilent(Hewlett-Packard) – Octal Cell Port Bypass Circuit without Clock and Data Recovery

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AV
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Figure 1. Block Diagram of HDMP-0480.
HDMP-0480 Block Diagram
AV Output
The Amplitude Valid (AV) block
detects if the incoming data on
FM_NODE[7]± is valid by exam-
ining the differential amplitude
of that input. The incoming data
is considered valid, and
FM_NODE[7]_AV is driven high,
as long as the amplitude is
greater than 400 mV (differential
peak-to-peak). FM_NODE[7]_AV
is driven low as long as the
amplitude of the input signal is
less than 100 mV (differential
peak-to-peak). When the ampli-
tude of the input signal is be-
tween 100-400 mV (differential
peak-to-peak), FM_NODE[7]_AV
is unpredictable.
BLL Output
All TO_NODE[n]± high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
Outputs on the HDMP-0480 are of
equal strength and can drive in
excess of 120 inches of FR-4 PCB
trace. Unused outputs should not
be left unconnected. Ideally,
unused outputs should have their
differential pins shorted together
with a short PCB trace. If trans-
mission lines are connected to
the output pins, the lines should
be differentially terminated with
an appropriate resistor. The value
of the termination resistor should
match the PCB trace differential
impedance.
EQU Input
All FM_NODE[n]± high-speed
differential inputs have an
Equalization (EQU) buffer to
offset the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs.
BYPASS[N]- Input
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0480. All BYPASS pins are
LVTTL and contain internal pull-
up circuitry. To bypass a port,
the appropriate BYPASS[n]- pin
should be connected to GND
through a 1kΩ resistor. Other-
wise, the BYPASS[n]- inputs
should be left to float. In this
case, the internal pull-up cir-
cuitry will force them high.
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