HCPL-315J Datasheet, PDF (18/21 Pages) Agilent(Hewlett-Packard) – 0.5 Amp Output Current IGBT Gate Drive Optocoupler

18
LED Drive Circuit
Considerations for Ultra
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
shown in Figure 29. The HCPL-
3150/315J improves CMR
performance by using a detector
IC with an optically transparent
Faraday shield, which diverts the
capacitively coupled current away
from the sensitive IC circuitry.
How ever, this shield does not
eliminate the capacitive coupling
between the LED and optocoup-
ler pins 5-8 as shown in
Figure 30. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 25), can achieve
15 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
7
Qg = 100 nC
6
Qg = 250 nC
Qg = 500 nC
5
4
V_CC = 19 V
V_EE = -9 V
3
2
1
0
0
20
40
60 80 100
Rg – GATE RESISTANCE – Ω
Figure 27. Energy Dissipated in the
HCPL-3150 for Each IGBT Switching
Cycle.
CMR with the LED On
(CMR_H)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED cur-
rent of 10 mA provides adequate
margin over the maximum I_FLH of
5 mA to achieve 15 kV/µs CMR.
CMR with the LED Off
(CMR_L)
A high CMR LED drive circuit
must keep the LED off
(V_F ≤ V_F(OFF)) during common
mode transients. For example,
during a -dV_CM/dt transient in
Figure 31, the current flowing
through C_LEDP also flows through
the R_SAT and V_SAT of the logic
gate. As long as the low state
voltage developed across the
logic gate is less than V_F(OFF), the
LED will remain off and no
common mode failure will occur.
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dV_CM/dt
transient, since all the current
flowing through C_LEDN must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMR_L
performance. Figure 33 is an
alternative drive circuit which,
like the recommended application
circuit (Figure 25), does achieve
ultra high CMR performance by
shunting the LED in the off state.
Under Voltage Lockout
Feature
The HCPL-3150/315J contains an
under voltage lockout (UVLO)
feature that is designed to protect
the IGBT under fault conditions
which cause the HCPL-3150/315J
supply voltage (equivalent to the
fully-charged IGBT gate voltage)
to drop below a level necessary to
keep the IGBT in a low resistance
state. When the HCPL-3150/315J
output is in the high state and the
supply voltage drops below the
HCPL-3150/315J V_UVLO- threshold
(9.5 <V_UVLO- <12.0), the
optocoupler output will go into
the low state with a typical delay,
UVLO Turn Off Delay, of 0.6 µs.
When the HCPL-3150/315J
output is in the low state and the
supply voltage rises above the
HCPL-3150/315J V_UVLO+
threshold (11.0 < V_UVLO+ < 13.5),
the optocoupler will go into the