HDMP-1685A Datasheet, PDF (16/21 Pages) Agilent(Hewlett-Packard) – 1.25 Gbps Four Channel SerDes with 5-pin DDR SSTL-2 Parallel Interface

HDMP-1685A TRx I/O Definition, continued
Name Pin Type
Signal
SO0+ R05
SO0- P05
SO1+ R07
SO1- P07
SO2+ P11
SO2- R11
SO3+ P13
SO3- R13
HS_ OUT Serial Data Outputs: High-speed outputs. These lines are active except when
PLUP is high, in which case these outputs are held static at logic 1.
SYNC R17
I-SSTL2
Enable Byte Sync Input: When high, turns on the internal byte sync functions to allow
clock synchronization to a comma character of positive disparity (0011111XXX). When
the line is low, the function is disabled and will not reset registers and clocks, or strobe
the SYN [0:3] lines.
SYN0 F02
SYN1 A04
SYN2 B10
SYN3 B15
O-SSTL2 Byte Sync Outputs: Active high outputs. Used to indicate detection of a comma
character of positive disparity (0011111XXX) when SYNC is enabled.
TC
K17 I-SSTL2 Transmit Byte Clock: This signal is used to latch transmit data for all channels
into the IC.
TX00 N01 I-SSTL2 Data Inputs: Four 5-pin data busses. TX [0:3] [0] are the first bits transmitted.
TX01 N02
TX02 N03
TX03 N04
TX04 M01
TX10 J01
TX11 J02
TX12 J03
TX13 J04
TX14 H01
TX20 G16
TX21 G15
TX22 G14
TX23 H17
TX24 H16
TX30 L17
TX31 L16
TX32 L15
TX33 L14
TX34 M17
VREFT P01 I-S
TX Parallel Interface SSTL_2 Reference Voltage: Voltage reference derived from
2 resistor network with V_DDQ (ASIC) as supply, as recommended in Figure 11.
VREFR D07 O-S
RX Parallel Interface SSTL_2 Reference Voltage: Provided by HDMP-1685A.
Drives the VREF input of the ASIC.
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