HDMP-1685A Datasheet, PDF (15/21 Pages) Agilent(Hewlett-Packard) – 1.25 Gbps Four Channel SerDes with 5-pin DDR SSTL-2 Parallel Interface

HDMP-1685A TRx I/O Definition
Name Pin
Type
Signal
CAP0 P09
C
CAP1 R09
Loop Filter Capacitor: A loop filter capacitor for the internal PLLs must be connected
across the CAP0 and CAP1 pins. (typical value = 0.1 µF)
PLUP N14
I-SSTL2
Parallel Loopback Enable Input: When set high, a high-speed serial signal from the
transmitter section’s serial output select block, reflecting TX data, is driven to the
receiver section’s serial input select block. RX data reflects this serial signal. Also
when in parallel loopback mode, the SO [0:3]+/- outputs are held static at logic 1.
RFCT R01
I-LVTTL LVTTL Reference Clock: RFCT is a 125 MHz clock signal supplied to the IC.
RC00 E01
RC01 E02
RC10 A05
RC11 B05
RC20 C10
RC21 D10
RC30 B16
RC31 B17
O-SSTL2 Receiver Byte Clocks: The receiver sections drive 125 MHz receive byte
clocks RC [0:3] [0:1].
RX00 D01
RX01 D02
RX02 E03
RX03 E04
RX04 C01
RX10 A06
RX11 B06
RX12 C06
RX13 D06
RX14 A07
RX20 B11
RX21 A12
RX22 B12
RX23 C12
RX24 D12
RX30 C17
RX31 D14
RX32 D15
RX33 D16
RX34 D17
O-SSTL2 Data Outputs: Four 5-pin data busses. RX [0:3] [0] are the first bits received.
SI0+
U04
SI0-
U03
SI1+
U07
SI1-
U06
SI2+
U11
SI2-
U10
SI3+
U14
SI3-
U13
HS_IN
Serial Data Inputs: High-speed inputs. Serial data are accepted from the SI [0:3]+/-
inputs except when PLUP is high.
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